1. Field of the Invention
The present invention relates to the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of borderless vias in intermetal dielectrics.
2. Description of the Related Art
As feature sizes in the production of integrated circuits approach 0.25 .mu.m and below, problems of packing density become increasingly difficult to overcome. The formation of borderless vias is one method to reduce metal pitch in and packing density of integrated circuits. However, it is exceedingly difficult to form borderless vias in conventional subtractive interconnect patterning. The major problem is that deep and narrow trenches are produced at the side of metal lines in via etching whenever vias are misaligned to the underlying metal lines. The trench depth is extremely difficult to control since it is common practice to excess plasma etch in via etch to ensure that via holes are completely open. Organic byproducts are produced in dielectric plasma etching when opening via holes. Those byproducts accumulated at the bottom of trenches cannot be effectively removed by oxygen-based plasma or ashing which are commonly used techniques to strip photoresist used in integrated circuit fabrication. Liquid organic chemicals, which are also commonly used to remove organic byproducts, often cause corrosion of metals from which interconnects are made. As a result, via resistance can be very high and, thus, the performance and reliability of integrated circuits degrade. In extreme cases, integrated circuits fail to function when via holes are totally blocked and vias become electrically open.
The cause of the above mentioned issues of conventional architectures is the lack of a etchstop or plasma etch selectivity when opening vias. These occur in different ways. Usually the same kind of inorganic dielectric is typically used for the via-level and metal-level inter-level dielectrics (IMD's). Even when two different kinds of inorganic dielectrics are used, as far as plasma etching for via holes is concerned, the difference between these two kinds of inorganic dielectrics is insignificant. As a result, via etch continues even when via holes are already fully opened as long as there is misalignment between via and the underlying interconnects or metal lines. The use of two different kinds of dielectrics, one inorganic and the other organic, have been used for the metal-level and the via-level IMD's, respectively, in some prior architectures. This architecture does not have the aforesaid disadvantage architectures since there is very high plasma etch selectivity between inorganic and organic dielectrics. However, its weakness is associated with the photoresist, which is commonly used for patterning, a key technique in integrated circuit fabrication. In conventional integration methods, both the photoresist and the organic IMD's are exposed at the completion of via etch. The organic via-level dielectric is attacked, resulting in deep trenches along the side of metal lines when removing the photoresist which is also organic.
According to the invention one ensures that the part of the via-level IMD, which is exposed to via etch plasma due to misalignment between via and metal lines, does not etch or only insignificantly etches in via openings and during resist removal following via etch. The invention provides borderless vias in integrated circuits. Two key elements are the use of dielectrics of significantly dissimilar plasma etch characteristics and that the dielectric immediately over metal lines is different from the dielectric at the sidewall of the metal lines. These objectives are achieved by dividing the metal-level IMD into two parts.
One dielectric forms a ledge between the metal lines and the rest of the metal-level IMD between the ledge and the metal lines is another dielectric. The two dielectrics are significantly different from each other in their plasma etch characteristics. One dielectric deposits on the sidewall of the metal lines in integrated circuit fabrication. Therefore, the dielectric immediately over metal lines needs to be selectively removed. One common technique is anisotropic plasma etchback. The timed etchback removes a certain amount of dielectric in the direction of plasma etching, which is perpendicular to the wafer in plasma etcher. There is only dielectric on the sidewall of metal lines at the completion of this etchback. In practice, a slightly excessive etch is executed to ensure that no Dielectric I is over metal lines and, thus, the surface of Dielectric I will be slightly below the top of metal lines. Dielectric over metal lines can alternatively be removed by chemical mechanical polishing (CMP), which removes only the dielectric over high-lying regions, the top of metal lines in this case. Metallic thin films can also be used for etchstop in via etch. However, metallic thin films cannot be left at the bottom of the gap between metal lines. Therefore, anisotropic etchback technique is used. The second objective can be achieved by adding a hardmask layer in between the resist and the organic dielectric for the via-level IMD so that either resist or the organic dielectric can be selectively removed. A hardmask is also necessary when the via-level IMD is inorganic and the etchstop, at the sidewall of metal lines, in via etch is organic. The hardmask can be either permanent or sacrificial. Dielectrics of low dielectric constant, k, value are used to minimize the inter-level and intra-level capacitances. Performance enhancement of integrated circuits is achieved with the implementation of new architectures according to this invention in conjunction with the use of dielectrics of low dielectric constant.